
import package_settings::*;

//-----------------------------------------------------------------------------
// dkl(n) = (v(n)   - v(n-k)) - (v(n-l) - v(n-k-l))
// p(n) = p(n-1) + dkl(n), n<=0
// r(n) = p(n)   + M*dkl(n)
// s(n) = s(n-1) + r(n),   n<=0
// M = 1/(exp(Tclk/tau) - 1)
//-----------------------------------------------------------------------------

module v2_filter (
//-----------------------------------------------------------------------------
// Input Ports
//-----------------------------------------------------------------------------
input wire 											    	clk,
input wire                            				    	reset,
input wire [SIZE_ADC_DATA-1:0]                              input_data,
//-----------------------------------------------------------------------------

// Output Ports
//-----------------------------------------------------------------------------
output reg    [SIZE_FILTER_DATA-1:0]                        output_data);
//-----------------------------------------------------------------------------
import v2_param::*;
//-----------------------------------------------------------------------------
reg           [SIZE_ADC_DATA*2+2:0]                         signal_delay [DELAY:0];
reg           [SIZE_ADC_DATA*2+2:0]                         dkl1;
reg           [SIZE_ADC_DATA*2+2:0]                         dkl2;
reg           [SIZE_ADC_DATA*2+2:0]                         dkl;
reg           [SIZE_ADC_DATA*2+2:0]                         md;
reg           [SIZE_ADC_DATA*2+2:0]                         p;
reg           [SIZE_ADC_DATA*2+2:0]                         r;
reg           [SIZE_ADC_DATA*2+2:0]                         s;
//-----------------------------------------------------------------------------
					
always @ (posedge clk or negedge reset)
	begin
		if (!reset)
		begin
			dkl1                                            <= 0;
			dkl2                                            <= 0;
			dkl                                             <= 0;
			md                                              <= 0;
			p                                               <= 0;
			r                                               <= 0;
			s                                               <= 0;	
//-----------------------------------------------------------------------------
			for (integer i = 0; i<=DELAY; i++)
			begin
				signal_delay[i]                            <= 0;
			end
			output_data                                    <= 0;
		end
		else
		begin
			signal_delay[0]                                <= input_data;
			for (integer i = 1; i<=DELAY; i++)
			begin
				signal_delay[i]                            <= signal_delay[i-1];
			end
			dkl1                                           <= signal_delay[0] - signal_delay[k];
			dkl2										   <= signal_delay[l] - signal_delay[k+l];
			dkl											   <= dkl1-dkl2;
			p                                              <= p + dkl;
			md  										   <= dkl * M;
			r											   <= p+md;
			s											   <= s+r;
			output_data                                    <= s >>> 7;
		end
	end	
endmodule
	
	